--周立功的开发板EasyFPGA030上的例程MUX_2的改写（语言：VHDL）
-- mux_2.vhd
library ieee;
use ieee.std_logic_1164.all;

entity mux_2 is
    port(sel: in std_logic;
         indat: in std_logic_vector(1 downto 0);
         led : out std_logic);
end entity mux_2;

architecture rtl of mux_2 is
begin
    process(sel,indat)
    begin
        if(sel = '0') then
            led <= indat(0);
        else
            led <= indat(1);
        end if;
    end process;
end architecture rtl;