-- LED.vhd
--周立功开发板EasyFPGA030的LED历程改写（语言：VHDL），已经在开发板上验证
library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_unsigned.all;

entity LED is
    port (clk: in std_logic;
          rst: in std_logic;
        ledout: out std_logic_vector(3 downto 0));
end  entity  LED;

architecture rtl of LED is
    signal  divclk: std_logic_vector(23 downto 0);
    signal  state:  std_logic_vector (4 downto 0);
    constant paramer: std_logic_vector(23 downto 0) := "101101110001101100000000";
begin
    process(rst,clk) is
    begin
        if(rst = '0') then
            ledout <= "1111";--灭
            divclk <= "000000000000000000000000";
            state <= "00000";
        elsif (clk'EVENT and clk='1') then
            if(divclk = paramer) then
                divclk <= "000000000000000000000000";
                if(state = "10001") then
                    state <= "00000";
                else
                    state <= state + "00001";
                end if;
             else
                divclk <= divclk + "000000000000000000000001";
             end if;
      

         case  state is
            when "00000"=> ledout <= "0111";
            when "00001"=> ledout <= "1011";
            when "00010"=> ledout <= "1101";
            when "00011"=> ledout <= "1110";
            when "00100"=> ledout <= "1110";
            when "00101"=> ledout <= "1101";
            when "00110"=> ledout <= "0111";
            when "00111"=> ledout <= "0011";
            when "01000"=> ledout <= "1100";
            when "01001"=> ledout <= "0110";
            when "01010"=> ledout <= "1001";
            when "01011"=> ledout <= "0001";
            when "01100"=> ledout <= "0010";
            when "01101"=> ledout <= "0100";
            when "01110"=> ledout <= "1000";
            when "01111"=> ledout <= "0000";
            when "10000"=> ledout <= "1111";
            when others=> ledout <= "0101";
        end case;
          end if;
    end process;
end architecture rtl;