module jishu(clk,clr,clken,q,co);
input clk,clr,clken;
output [3:0]q;
output co;
reg[3:0]q;
reg co;
always@(posedge clr or posedge clk)
 begin
 if(clr) q<=0;
 else if(!clken) q<=q;
 else
 if(q==9)
 begin q=0;co<=1; end
 else
 begin q=q+4'd1;
 co=0;
 end
 end
endmodule