module jishu(clk,clr,clken,q,co); input clk,clr,clken; output q; output co; reg q; reg co; always@(posedge clr or posedge clk)  begin  if(clr) q<=0;  else if(!clken) q<=q;  else  if(q==9)  begin q=0;co<=1; end  else  begin q=q+4'd1;