-- statemachine.vhd
-- state_machine.vhd
--周立功的开发板EasyFPGA030状态机用VHDL程序改写；
--已经验证。
--状态图见周立功的开发板EasyFPGA030的例程。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity statemachine  is
    port(rst:   in std_logic;                   -- 复位输入，低电平有效
         clk:   in std_logic;                   --时钟输入，48M
         sel: in std_logic;                     --流水灯方向控制，0：按下，1：放开
         q:     out std_logic_vector(3 downto 0)--输出，0：点亮，1：熄灭
         );
end entity statemachine;

architecture  rtl of statemachine is
    signal    div_clk: std_logic;
    signal    clk_cnt: std_logic_vector(25 downto 0);
    constant  clk_value: std_logic_vector(25 downto 0):= "10110111000110110000000000";
    constant  st1:  std_logic_vector(1 downto 0) := "00";--状态机状态1参数定义
    constant  st2:  std_logic_vector(1 downto 0) := "01";--状态机状态2参数定义
    constant  st3:  std_logic_vector(1 downto 0) := "10";--状态机状态3参数定义
    constant  st4:  std_logic_vector(1 downto 0) := "11";--状态机状态4参数定义
    signal    sts:  std_logic_vector(1 downto 0);

begin
    div_clk_0: process(rst,clk) is
    begin
        if(rst = '0') then
            clk_cnt <= "00000000000000000000000000";
            div_clk <= '0';
        elsif (clk'EVENT and clk='1') then
            if (clk_cnt = clk_value - 1) then
                clk_cnt <= "00000000000000000000000000";
                div_clk <= not div_clk;
            else
                clk_cnt <= clk_cnt + "00000000000000000000000001";
            end if;
         end if;
    end process div_clk_0;

    state_0: process(rst,div_clk) is
    begin
        if (rst = '0') then
            q <= "0000";
            sts <= st1;
        elsif (div_clk'EVENT and div_clk='1') then
            case (sts) is
                when st1 => q <= "1110"; --第一个状态第一位输出为0
                            if (sel = '1') then
                                sts <= st2;      --根据sel判断流水灯方向
                            else
                                sts <= st4;
                            end if;
                when st2 => q <= "1101";    --第二个状态第二位输出0
                            if(sel = '1') then
                                 sts <= st3;
                            else
                                 sts <= st1;
                            end if;
                when st3 => q <= "1011";     --第三个状态第三位输出0
                            if (sel = '1') then
                                sts <= st4;
                            else
                                sts <= st2;
                            end if;
                when st4 => q <= "0111";--第4个状态第四位输出为0
                            if(sel = '1') then
                                sts <= st1;
                            else
                                sts <= st3;
                            end if;
               
            end case;
        end if;
    end process state_0;
end architecture rtl;