--beinghu2网友发的PWM波形生成器,我没有在周立功的开发板EasyFPGA030上验证,我认为这个编程有其优势:
--可以生成随输入量PWM_in变化而正脉宽变化的波形;
--有兴趣的朋友可以试验一下。
-- hds header_start
-- hds header_end
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- hds header_end
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
port (
clk : in std_logic;
sysrst : in std_logic;
PWM_in : in std_logic_vector (7 downto 0) := "00000000";
PWM_out : out std_logic
);
end PWM;
port (
clk : in std_logic;
sysrst : in std_logic;
PWM_in : in std_logic_vector (7 downto 0) := "00000000";
PWM_out : out std_logic
);
end PWM;
-- hds interface_end
architecture PWM_arch of PWM is
signal PWM_Accumulator : std_logic_vector(8 downto 0);
begin
process(clk,sysrst)
begin
if sysrst='1' then
PWM_Accumulator<=(others=>'0');
elsif rising_edge(clk) then
PWM_Accumulator <= ("0" & PWM_Accumulator(7 downto 0)) + ("0" & PWM_in);
end if;
end process;
PWM_out <= PWM_Accumulator(8);
end PWM_arch;
end PWM_arch;
发表评论 评论 (0 个评论)