-- ledcmp.vhd
--周立功的开发板EasyFPGA030用VHDL写的程序，已经调试通过；
--本程序和LED.vhd相比，采用了component结构

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity  ledcmp is
    port(clk: in std_logic;
         rst: in std_logic;
         ledout: out std_logic_vector(3 downto 0));
end entity ledcmp;

architecture  rtl of ledcmp is
    component   divclk
        port   (clk: in std_logic;
               rst: in std_logic;
               divclkout: out std_logic);
    end component;

    signal  clkout: std_logic;
    signal  state: std_logic_vector(4 downto 0);
begin
    div: component divclk
    port map(clk=>clk,rst=>rst,divclkout=>clkout);

    process(rst,clkout)
    begin
        if(rst = '0') then
            state <= "00000";
            ledout <= "0000";
        elsif(clkout'EVENT and clkout = '1') then
            if(state = "10001") then
                state <= "00000";
            else
                state <= state + 1;
            end if;
       

        case  state is
            when "00000"=> ledout <= "0111";
            when "00001"=> ledout <= "1011";
            when "00010"=> ledout <= "1101";
            when "00011"=> ledout <= "1110";
            when "00100"=> ledout <= "1110";
            when "00101"=> ledout <= "1101";
            when "00110"=> ledout <= "0111";
            when "00111"=> ledout <= "0011";
            when "01000"=> ledout <= "1100";
            when "01001"=> ledout <= "0110";
            when "01010"=> ledout <= "1001";
            when "01011"=> ledout <= "0001";
            when "01100"=> ledout <= "0010";
            when "01101"=> ledout <= "0100";
            when "01110"=> ledout <= "1000";
            when "01111"=> ledout <= "0000";
            when "10000"=> ledout <= "1111";
            when others=> ledout <= "0101";
        end case;
    end if;
    end process;
end architecture rtl;  

-- divclk.vhd
--分频电路
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity  divclk is
     port     (clk: in std_logic;
               rst: in std_logic;
               divclkout: out std_logic);
end entity divclk;

architecture rtl of divclk is
    constant paramer: std_logic_vector(23 downto 0) := "101101110001101100000000";
    signal divsum: std_logic_vector(23 downto 0);
    signal clktmp: std_logic;
begin
    divclkout <= clktmp;

    process(rst,clk) is
    begin
        if(rst = '0') then
            divsum <= "000000000000000000000000";
            clktmp <= '0';
        elsif(clk'EVENT and clk = '1') then
            if(divsum = paramer) then
                divsum <= "000000000000000000000000";
                clktmp <= not clktmp;
            else
                divsum <= divsum + 1;
            end if;
        end if;
    end process;
end architecture rtl;