VHDL测试平台设计_文件的操作
本文讨论VHDL测试平台设计中的文件操作,文件操作的好处是可以将测试结果以文件的形式进行保存以便日后观。本文的设计实体功能是实现8位的加法器,代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_8bit is
port(clk : in std_logic;
done : in std_logic_vector(7 downto 0);
dtwo : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(8 downto 0));
end adder_8bit;
architecture behave of adder_8bit is
begin
process(clk)
begin
if clk'event and clk = '1' then
sum <= ('0' & done) + ('0' & dtwo);
end if;
end process;
end behave;
测试平台为,代码中显示了文件的操作方法:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity adder_8bit_tb is
end adder_8bit_tb;
architecture behave of adder_8bit_tb is
component adder_8bit
port(clk : in std_logic;
done : in std_logic_vector(7 downto 0);
dtwo : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(8 downto 0));
end component;
signal done : std_logic_vector(7 downto 0) := (others => '0');
signal dtwo : std_logic_vector(7 downto 0) := (others => '0');
signal sum : std_logic_vector(8 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal IsOK : boolean := false;
signal result : integer := 0;
begin
dut : adder_8bit
port map(clk => clk,
done => done,
dtwo => dtwo,
sum => sum);
clk <= not clk after 20ns;
Process
--定义输入数据的文件
file input_file : text open read_mode is "test_data.dat";
--定义行变量,一个用来输入,一个用来输出
variable vline, wline : line;
variable good : boolean;
variable temp_one : integer;
variable temp_two : integer;
variable temp_sum : integer;
--定义输出数据文件
file output_file : text open write_mode is "sum_data.dat";
begin
wait until clk = '1' and clk'event;
--从文件中读入一行
readline(input_file, vline);
--从行变量中读取数据
read(vline, temp_one, good);
read(vline, temp_two, good);
if(good) then
done <= conv_std_logic_vector(temp_one, 8);
dtwo <= conv_std_logic_vector(temp_two, 8);
else
assert false report "End of Reading Input File!"
severity error;
end if;
temp_sum := conv_integer(sum);
--把结果写入行变量
write(wline, temp_sum);
--把行变量写入文件
writeline(output_file, wline);
end process;
end behave;
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