1 module CRC5_D8;
 2 
 3   // polynomial: (0 2 5)
 4   // data width: 8
 5   // convention: the first serial bit is D[7]
 6     [4:0] nextCRC5_D8;
 7 
 8     input [7:0] Data;
 9     input [4:0] crc;
10     reg [7:0] d;
11     reg [4:0] c;
12     reg [4:0] newcrc;
13   begin
14     d = Data;
15     c = crc;
16 
17     newcrc[0] = d[6] ^ d[5] ^ d[3] ^ d[0] ^ c[0] ^ c[2] ^ c[3];
18     newcrc[1] = d[7] ^ d[6] ^ d[4] ^ d[1] ^ c[1] ^ c[3] ^ c[4];
19     newcrc[2] = d[7] ^ d[6] ^ d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[3] ^ c[4];
20     newcrc[3] = d[7] ^ d[4] ^ d[3] ^ d[1] ^ c[0] ^ c[1] ^ c[4];
21     newcrc[4] = d[5] ^ d[4] ^ d[2] ^ c[1] ^ c[2];
22     nextCRC5_D8 = newcrc;
23   end
24   end
25  endmodule
26  

 1 // CRC module for
 2  //       data[7:0]
 3  //       crc[4:0]=1+x^2+x^5;
 4  //
 5 module crc(
 6         input [7:0] data_in,
 7         input        crc_en,
 8         output [4:0] crc_out,
 9         input        rst,
10         input        clk);
11 
12         reg [4:0] lfsr_q,
13                    lfsr_c;
14         assign crc_out = lfsr_q;
15         always @(*) begin
16                 lfsr_c[0] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[3] ^ data_in[0] ^ dat
17 a_in[3] ^ data_in[5] ^ data_in[6];
18                 lfsr_c[1] = lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[1] ^ dat
19 a_in[4] ^ data_in[6] ^ data_in[7];
20                 lfsr_c[2] = lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[0] ^ dat
21 a_in[2] ^ data_in[3] ^ data_in[6] ^ data_in[7];
22                 lfsr_c[3] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ data_in[1] ^ dat
23 a_in[3] ^ data_in[4] ^ data_in[7];
24                 lfsr_c[4] = lfsr_q[1] ^ lfsr_q[2] ^ data_in[2] ^ data_in[4] ^ da
25 ta_in[5];
26 
27 
28         end // always
29 
30         always @(posedge clk, posedge rst) begin
31                 if(rst) begin
32                         lfsr_q  <= {5{1'b1}};
33                 end
34                 else begin
35                         lfsr_q  <= crc_en ? lfsr_c : lfsr_q;
36                 end
37         end // always
38 endmodule // crc
39