同步复位敏感的是时钟信号；异步复位敏感的是复位信号和时钟信号；其VHDL描述是：
--同步复位
library ieee;
use ieee.std_logic_1164.all;
entity tst is
....
end entity tst;
architecture rtl of tst is
...
begin
process(clk)
begin
if(clk'EVENT and clk='1') then
if(reset='1') then
q<= '0';
else
q<=d_in;
.....
end if;
................
end if;
end process;
......
end architecture rtl;
--异步复位
library ieee;
use ieee.std_logic_1164.all;
entity tst is
....
end entity tst;
architecture rtl of tst is
...
begin
process(reset,clk)
begin
if(reset='1') then
q<='0';
elsif(clk'EVENT and clk='1') then
q <= d_in;
.......
end if;
end process;
end architecture rtl;
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